Conventional integrated circuit manufacturing processes typically involve the creation of openings (often termed "vias" or "windows") in a dielectric layer. The openings are often subsequently filled with a conductive material, such as a metal or polysilicon, which provides electrical connection through the dielectric. For example, in many MOSFET fabrication processes, after the source, gate and drain have been formed, a dielectric is deposited in a blanket manner over the transistor. An opening is created above some or all of the sources and drains. A conductive material, for example, aluminum or tungsten is deposited within the opening, thus contacting the source or drain. The conductive material in the opening provides a path for electrical contact between the source or drain and a conductive (often metallic) runner on the upper surface of the dielectric.
In multilevel integrated circuits, additional layers of dielectric are deposited with openings formed therein. Conductive material is formed within these openings. The conductive material serves to provide the electrical contact between runners beneath the additional dielectric layer and runners above the additional dielectric layer.
As the dimensions of integrated circuits continue to shrink, the linewidths of the conductors also continue to decrease, i.e., the conductors become narrower. However, stresses imposed upon the conductive runners also increase, thus causing stress-related electromigration failures (or other types of failures) in narrow runners which may lead to undesirable open circuits.